The present invention relates to a transmitter-receiver circuit and also relates to a semiconductor integrated circuit device including the transmitter-receiver circuit. More particularly, the present invention relates to transmitter-receiver circuit and semiconductor integrated circuit device suitable for a wireless communication unit using the same frequency as both transmission frequency and reception frequency.
In recent years, size, weight and price of various wireless communication units, e.g., portable cellular phone units for radio communication, have been drastically reduced, and the number of users thereof has been rapidly increasing. In conventional communication systems, a system configuration requiring distinct frequencies for transmission and reception has been adopted so far. On the other hand, in order to satisfy the needs of an even larger number of users, digital implementation has been gradually applied to these units. While two distinct frequencies per line have been required conventionally, such a digital wireless communication unit can perform transmission and reception with the same frequency by dividing transmission and reception in a time-division manner.
Even in such a wireless communication unit utilizing digital implementation, however, various circuits in a wireless circuit section, including a transmitter amplifier, a low-noise receiver amplifier and a transmission/reception mode switch for switching transmission and reception, are still implemented by conventional circuits. Thus, it is an important problem to develop downsized transmitter-receiver circuits and, in particular, semiconductor integrated circuit integrated with these circuits that are suitably applicable to brand-new digital implementation.
Also, a circuit including gallium-arsenide field effect transistors (hereinafter, simply referred to as xe2x80x9cGaAs FETsxe2x80x9d), having low-voltage, high-efficiency and low-noise operating characteristics and high-isolation characteristics, are often used for a transmitter amplifier, a low-noise receiver amplifier and a transmission/reception mode switch in a transmitter-receiver circuit for a wireless communication unit of a digital type.
Hereinafter, an example of a conventional transmitter-receiver circuit will be described with reference to the drawings.
FIG. 11 illustrates a configuration of a conventional digital transmitter-receiver circuit using FETS. In FIG. 11, 110 denotes a transmitter amplifier for amplifying an input signal to be transmitted and then outputting the amplified signal. 120 denotes a low-noise receiver amplifier for amplifying an input received signal and then outputting the amplified signal. 130 denotes a mode switch for switching transmission state and reception state in a time-division manner. 140 denotes a first matching circuit for matching the impedance of the input received signal with the input impedance of the low-noise receiver amplifier 120. 150 denotes a second matching circuit for matching the output impedance of the transmitter amplifier 110 with predetermined impedance. 160 denotes a third matching circuit for matching the output impedance of a FET 112 on the first stage with the input impedance of a FET on the second stage. 171 denotes first coupling capacitance for ac coupling the transmitter amplifier 110 with the second matching circuit 150. 172 denotes second coupling capacitance for ac coupling the mode switch 130 with the first matching circuit 140. 173 denotes a first interconnection, having characteristic impedance of 500, for connecting the mode switch 130 to the second matching circuit 150. 174 denotes a second interconnection, having characteristic impedance of 50xcexa9, for connecting the mode switch 130 to the first matching circuit 140. 175 denotes a third interconnection, having characteristic impedance of 50xcexa9, for connecting the mode switch 130 to an antenna 180 used both for transmission and reception.
In the transmitter amplifier 110 shown in FIG. 11, 111 denotes an input terminal, through which a signal to be transmitted is input. 112 denotes a FET on the first stage, of which the gate electrode is provided with the input signal to be transmitted and the source is grounded. 113 denotes a first power supply terminal connected to the drain electrode of the FET 112 on the first stage. 114 denotes a FET on the second stage, of which the gate electrode is provided with the signal to be transmitted via the third matching circuit 160 and the source is grounded. 115 denotes a second power supply terminal connected to the drain electrode of the FET 114 on the second stage. 116 denotes an output terminal connected to the drain electrode of the FET 114 on the second stage.
In the low-noise receiver amplifier 120 shown in FIG. 11, 121 denotes an input terminal, through which a received signal is input via the first matching circuit 140. 122 denotes a low-noise FET, of which the gate electrode is provided with the received signal and the source is grounded. 123 denotes an output terminal connected to the drain electrode of the low-noise FET 122.
In the mode switch 130 shown in FIG. 11, 131 denotes an input terminal on the transmission side connected to the second matching circuit 150. 132 denotes an input/output terminal on the antenna side for outputting a signal to be transmitted, which has been amplified by the transmitter amplifier 110 and then input thereto via the second matching circuit 150 during transmission, to the antenna 180, and for receiving the received signal that has been received by the antenna 180 during reception. 133 denotes an output terminal on the reception side, through which the received signal input from the input/output terminal 132 on the antenna side is output. 134A denotes first switch-control-signal input terminals for controlling a first switching FET 135 and a third switching FET 137. 134B denotes second switch-control-signal input terminals for controlling a second switching FET 136 and a fourth switching FET 138.
In the first matching circuit 140 shown in FIG. 11, 141 denotes an input terminal connected to the output terminal 133 on the reception side of the mode switch 130 via the second coupling capacitance 172. 142 denotes an output terminal connected to the input terminal 121 of the low-noise receiver amplifier 120. 143 denotes a first inductor, one end of which is connected to the input terminal 141 and the other end of which is grounded, for constituting the first matching circuit 140. 144 denotes a second inductor, one end of which is connected to the input terminal 141 and the other end of which is connected to the output terminal 142, for constituting the first matching circuit 140.
In the second matching circuit 150 shown in FIG. 11, 151 denotes an input terminal connected to the output terminal 116 of the transmitter amplifier via the first coupling capacitance 171. 152 denotes an output terminal connected to the input terminal 131 on the transmission side of the mode switch 130. 153 denotes a first capacitor, one end of which is connected to the input terminal 151 and the other end of which is grounded, for constituting the second matching circuit 150. 154 denotes an inductor, one end of which is connected to the input terminal 151 and the other end of which is connected to a second capacitor 155, for constituting the second matching circuit 150. 155 denotes the second capacitor, one end of which is connected to the inductor 154 and the other end of which is connected to the output terminal 152, for constituting the second matching circuit 150.
In the third matching circuit 160 shown in FIG. 11, 161 denotes a first capacitor, one end of which is connected to the drain electrode of the FET 112 on the first stage in the transmitter amplifier 110 and the other end of which is connected to an inductor 162, for constituting the third matching circuit 160. 162 denotes the inductor, one end of which is connected to the first capacitor 161 and the other end of which is connected to the gate electrode of the FET 114 on the second stage in the transmitter amplifier 110, for constituting the third matching circuit 160. 163 denotes a second capacitor, one end of which is connected to the inductor 162 and the gate electrode of the FET 114 on the second stage and the other end of which is grounded, for constituting the third matching circuit 160.
Hereinafter, the operation of the transmitter-receiver circuit having the above-described configuration will be described.
First, the operation during reception will be described.
A less intense received signal, input via the antenna 180, passes through the third interconnection 175 having characteristic impedance of 50xcexa9 and is input to the input/output terminal 132 on the antenna side of the mode switch 130. At this point in time, in the mode switch 130, the first switching FET 135 and the third switching FET 137 have been turned ON responsive to the control signal input through the first switch-control-signal input terminals 134A, while the second switching FET 136 and the fourth switching FET 138 have been turned OFF responsive to the control signal input through the second switch-control-signal input terminals 134B. Thus, the input signal is selectively directed to the low-noise receiver amplifier 120 via the third switching FET 137, which has been turned ON. On the other hand, the circuit section including the transmitter amplifier 110 is electrically isolated from the circuit section including the low-noise receiver amplifier 120, because the second switching FET 136 has been turned OFF. Also, the former circuit section is short-circuited, because the first switching FET 135 has been turned ON.
The signal switched by the third switching FET 137 in the conductive state is output through the output terminal on the reception side of the mode switch 130, passed through the second interconnection 174 having characteristic impedance of 50xcexa9 and the second coupling capacitance 172 and then input to the first matching circuit 140. Then, impedance matching is performed by the first inductor 143 and the second inductor 144 of the first matching circuit 140. Thereafter, the signal is input to the input terminal 121 of the low-noise receiver amplifier 120. The received signal input to the low-noise receiver amplifier 120 is amplified by the low-noise FET 122 and the amplified signal is output through the output terminal 123.
Next, the operation during transmission will be described.
First, modulated signal to be transmitted is input to the input terminal Ill of the transmitter amplifier 110. Power amplification on the first stage is performed by the FET 112 on the first stage. Impedance conversion is performed by the third matching circuit 160. Then, the signal is input to the FET 114 on the second stage. The power of the signal is amplified by the FET 114 on the second stage so as to reach predetermined power. The amplified signal to be transmitted is input to the second matching circuit 150 via the first coupling capacitance 171. The characteristic impedance thereof is converted to be 50xcexa9. And then the signal is input to the input terminal 131 on the transmission side of the mode switch 130 through the first interconnection 173 having characteristic impedance of 50xcexa9.
At this point in time, in the mode switch 130, the second switching FET 136 and the fourth switching FET 138 have been turned ON responsive to the control signal input through the second switch-control-signal input terminals 134B, while the first switching FET 135 and the third switching FET 137 have been turned OFF responsive to the control signal input through the first switch-control-signal input terminals 134A. Thus, the input signal to be transmitted is selectively directed to the antenna 180 via the second switching FET 136, which has been turned ON. On the other hand, the circuit section including the low-noise receiver amplifier 120 is electrically isolated from the circuit section including the transmitter amplifier 110, because the third switching FET 137 has been turned OFF. Also, the former circuit section is short-circuited, because the fourth switching FET 138 has been turned ON.
The amplified signal to be transmitted passes through the second switching FET 136 in the conductive state and the third interconnection 175 having characteristic impedance of 50xcexa9 and is input to the antenna 180 so as to be output through the antenna 180 as radio waves.
The above-described conventional transmitter-receiver circuit, however, had a problem in that the loss of a signal passing through the mode switch 130 is large. In particular, the loss of a signal to be transmitted becomes an issue because such a signal requires high power. Thus, it is necessary to improve the performance of a through switching FET on the transmission side. In general, in order to reduce the pass loss, a switching FET having a large gate length is required. In addition, if switching FETs of such a large size are integrated, then the chip area is increased to such a degree that the area occupied by the mode switch 130 becomes substantially equal to the area of the transmitter amplifier 110. Thus, problems are present in that downsizing and cost-reduction thereof are hard to realize.
The present invention can solve the above-described conventional problems all at once, and has objects of reducing the power consumption by eliminating the pass loss caused by the mode switch on the signal to be transmitted and downsizing a wireless communication unit by reducing the area occupied by the mode switch in the transmitter-receiver circuit.
In order to accomplish the above-described objects, the present invention connects a transmitter amplifier to an antenna without interposing any mode switch therebetween by matching the inputs to a receiver amplifier while using, in combination, the output impedance of the transmitter amplifier during the OFF state and the output impedance to the receiver amplifier.
A transmitter-receiver circuit for a wireless communication unit according to the present invention includes: a transmitter amplifier for amplifying and outputting an input signal to be transmitted; a receiver amplifier for amplifying and outputting an input received signal; and a mode switch, connected to an antenna used for both transmission and reception, for switching a transmission state where the signal to be transmitted, which has been output by the transmitter amplifier, is output to the antenna and a reception state where the received signal, to be input to the receiver amplifier, is input through the antenna. The transmitter amplifier includes: an amplifying FET, having a gate electrode connected to an input terminal of the signal to be transmitted, a drain electrode connected to a power supply terminal and a source electrode grounded; a matching circuit, connected between the drain electrode of the FET and the antenna, for matching output impedance of the FET with impedance on the antenna side; a control terminal connected to the gate electrode of the FET; and an output terminal directly connected to the antenna without passing through the mode switch.
In the transmitter-receiver circuit for a wireless communication unit, since the output terminal of the transmitter amplifier is directly connected to the antenna without passing through the mode switch during transmission, the pass loss, ordinarily caused by a switch on a signal to be transmitted, can be eliminated. As a result, the power consumption can be reduced. On the other hand, during reception, since a control terminal connected to the gate electrode of the FET of the transmitter amplifier is provided, the circuit section on the transmission side is short-circuited by applying a predetermined voltage to the gate electrode and using the FET having the grounded source as resistance. As a result, a mode switch on the transmission side, which has conventionally been required, is no longer necessary. In other words, a mode switch on the reception side may be constituted by only one switching device, and thus the area occupied by the mode switch in the entire circuit can be reduced. As a result, the overall size of the transmitter-receiver circuit can be reduced.
Another transmitter-receiver circuit for a wireless communication unit according to the present invention includes: a transmitter amplifier for amplifying and outputting an input signal to be transmitted; a receiver amplifier for amplifying and outputting an input received signal; and a mode switch, connected to an antenna used for both transmission and reception, for switching a transmission state where the signal to be transmitted, which has been output by the transmitter amplifier, is output to the antenna and a reception state where the received signal, to be input to the receiver amplifier, is input through the antenna. The transmitter amplifier includes: an amplifying FET, having a gate electrode connected to an input terminal of the signal to be transmitted, a drain electrode connected to a power supply terminal and a source electrode grounded; a matching circuit, connected between the drain electrode of the FET and the antenna, for matching output impedance of the FET with impedance on the antenna side; a control terminal connected to the gate electrode of the FET; and an output terminal directly connected to the antenna without passing through the mode switch. The input terminal on the antenna side of the mode switch is connected to a terminal of the matching circuit, which is different from the output terminal of the signal to be transmitted of the matching circuit.
In the transmitter-receiver circuit for a wireless communication unit, since the output terminal of the transmitter amplifier is directly connected to the antenna without passing through the mode switch during transmission, the pass loss, ordinarily caused by a switch on a signal to be transmitted, can be eliminated. As a result, the power consumption can be reduced. On the other hand, during reception, since a control terminal connected to the gate electrode of the FET of the transmitter amplifier is provided, the circuit section on the transmission side is short-circuited by applying a predetermined voltage to the gate electrode and using the FET having the grounded source as resistance. As a result, a mode switch on the transmission side, which has conventionally been required, is no longer necessary. In other words, a mode switch on the reception side may be constituted by only one switching device, and thus the area occupied by the mode switch in the entire circuit can be reduced. As a result, the overall size of the transmitter-receiver circuit can be reduced. Moreover, where a receiving matching circuit for matching the impedance of the received signal with the input impedance of the receiver amplifier is provided between the mode switch and the receiver amplifier, a terminal allowing for optimization of the circuit constant of the receiving matching circuit can be selected. As a result, since the design flexibility of the receiving matching circuit can be increased, the size of the receiving matching circuit can be reduced.
A semiconductor integrated circuit device according to the present invention, includes: a semiconductor substrate; a transmitter amplifier, formed on the semiconductor substrate, for amplifying and outputting an input signal to be transmitted; a receiver amplifier, formed on the semiconductor substrate, for amplifying and outputting an input received signal; and a mode switch, formed on the semiconductor substrate and connected to an input/output terminal on an antenna side used for both transmission and reception, for switching a transmission state where the signal to be transmitted, which has been output by the transmitter amplifier, is output to the input/output terminal on the antenna side and a reception state where the received signal, to be input to the receiver amplifier, is input through the input/output terminal on the antenna side. The transmitter amplifier includes: an amplifying FET, having a gate electrode connected to an input terminal of the signal to be transmitted, a drain electrode connected to a power supply terminal and a source electrode grounded; a matching circuit, connected between the drain electrode of the FET and the input/output terminal on the antenna side, for matching output impedance of the FET with impedance on the antenna side; a control terminal connected to the gate electrode of the FET; and an output terminal directly connected to the input/output terminal on the antenna side without passing through the mode switch.
In the semiconductor integrated circuit device, since the output terminal of the transmitter amplifier is directly connected to the input/output terminal on the antenna side without passing through the mode switch during transmission, the pass loss, ordinarily caused by a switch on a signal to be transmitted, can be eliminated. As a result, the power consumption can be reduced. On the other hand, during reception, since a control terminal connected to the gate electrode of the FET of the transmitter amplifier is provided, the circuit section on the transmission side is short-circuited by applying a predetermined voltage to the gate electrode and using the FET as resistance. As a result, a mode switch on the reception side may be constituted by only one switching device, and thus the area occupied by the mode switch in the entire circuit can be reduced. Consequently, features advantageous for high integration can be attained and the device can be downsized.
Another semiconductor integrated circuit device according to the present invention includes: a semiconductor substrate; a transmitter amplifier, formed on the semiconductor substrate, for amplifying and outputting an input signal to be transmitted; a receiver amplifier, formed on the semiconductor substrate, for amplifying and outputting an input received signal; and a mode switch, formed on the semiconductor substrate and connected to an input/output terminal on an antenna side used for both transmission and reception, for switching a transmission state where the signal to be transmitted, which has been output by the transmitter amplifier, is output to the input/output terminal on the antenna side and a reception state where the received signal, to be input to the receiver amplifier, is input through the input/output terminal on the antenna side. The transmitter amplifier includes: an amplifying FET, having a gate electrode connected to an input terminal of the signal to be transmitted, a drain electrode connected to a power supply terminal and a source electrode grounded; a matching circuit, connected between the drain electrode of the FET and the input/output terminal on the antenna side, for matching output impedance of the FET with impedance on the antenna side; a control terminal connected to the gate electrode of the FET; and an output terminal directly connected to the input/output terminal on the antenna side without passing through the mode switch. The input terminal on the antenna side of the mode switch is connected to a terminal of the matching circuit, which is different from the output terminal of the signal to be transmitted of the matching circuit.
In the semiconductor integrated circuit device, since the output terminal of the transmitter amplifier is directly connected to the input/output terminal on the antenna side without passing through the mode switch during transmission, the pass loss, ordinarily caused by a switch on a signal to be transmitted, can be eliminated. As a result, the power consumption can be reduced. On the other hand, during reception, since a control terminal connected to the gate electrode of the FET of the transmitter amplifier is provided, the circuit section on the transmission side is short-circuited by applying a predetermined voltage to the gate electrode and using the FET as resistance. As a result, a mode switch on the transmission side is no longer necessary. In other words, a mode switch on the reception side may be constituted by only one switching device, and thus the area occupied by the mode switch in the entire circuit can be reduced. Moreover, where a receiving matching circuit for matching the impedance of the received signal with the input impedance of the receiver amplifier is provided between the mode switch and the receiver amplifier, a terminal allowing for optimization of the circuit constant of the receiving matching circuit can be selected. As a result, since the design flexibility of the receiving matching circuit can be increased, the size of the receiving matching circuit can be reduced. Consequently, the size of the device can be further reduced.